1. Field of the Invention
The present invention relates to a bipolar transistor for use in an integrated circuit, and more particularly to a bipolar transistor which has an improved operating characteristics in a moderate-injection region.
2. Description of the Related Art
To manufacture a semiconductor device of a high integration density, such as VLSI (Very Large-Scale Integration) circuit, bipolar transistors must be used which operate at high speed and consumes a little power. In recent years, various structures for such bipolar transistors, and various methods of manufacturing such bipolar transistors have been proposed.
There are two points essential to a high-speed, low-power consumption bipolar transistor. First, the transistor should have a shallow vertical junction. Second, the transistor should be small in terms of the horizontal direction. Detrimental to the operating speed of a bipolar transistor is the so-called "Kirk effect" the phenomenon that the apparent depth of the base region increases in proportion to the current injected to the transistor. Hence, it is important to suppress the Kirk effect in order to raise the operating speed of the bipolar transistor.
Of the prior-art publications concerned with high-speed, low-power consumption bipolar transistors, a few will be discussed which seem to be relevant to this invention.
Japanese Patent Publication No. 51-5763 discloses a planer bipolar transistor. As is shown in FIG. 1, this bipolar transistor comprises emitter region 1, inner base region 2a, outer base region 2b, inner collector region 3a, outer collector region 3b, and buried collector region 3c. The structures of collector regions 3a, 3b, and 3c characterize this bipolar transistor. Internal collector region 2a is located below emitter region 1 and has the same width as emitter region 1. External collector region 3b has a higher resistance than inner collector region 3a, and surrounds inner collector region 3a. Collector regions 3a and 3b have their upper surfaces flush with each other. The buried collector region 3c has a low resistance and a high impurity concentration, is located right below inner collector region 3a and outer collector region 3b, and contacting both collector regions 3a and 3b.
Konaka et al. disclose a planer bipolar transistor of the structure shown in FIG. 2, in their thesis A 20ps/G Si Bipolar IC Using Advanced SST with Collector Ion Implantation, the proceedings for 19th Conference on Solid State Devices and Materials, pp. 331-334. In FIG. 2, the same reference numerals are used to denote the same elements as those shown in FIG. 1. This bipolar transistor also comprises inner collector region 3a, outer collector region 3b, and buried collector region 3c. The transistor is different from the transistor shown in FIG. 1 in two respects. First, inner collector region 3a and buried collector region 3c are set apart from each other, and outer collector region 3b is interposed between these regions 3a and 3c. Secondly, inner collector region 3a has a width broader than that of emitter region 1.
In either bipolar transistor, inner collector region 3a serves to suppress the Kirk effect. More precisely, region 3a, which has a relatively high impurity concentration, prevents the holes accumulated in inner base region 2a from moving into collector region 3b to cause the Kirk effect.
Both conventional bipolar transistors described above are disadvantageous in the following respects.
First, these transistors operate at low speed in a moderate-injection region. This is because inner collector region 3a having a relatively high impurity concentration contacts inner base region 2a, and the base/collector junction has a larger junction capacitance than in the case where internal collector region 3a is not interposed between regions 2b and 3b.
Second any circuit including transistors of either type has a long delay time. The cross section of the boundary between inner base region 2a and outer base region 2b depends upon the height of inner collector region 3a. To reduce the depth of inner base region 2a, the upper surface of inner collector region 3a must be raised. The higher the upper surface of region 3a, the narrower the carrier path between inner base region 2a and outer base region 2b. Hence, when the upper surface of region 3a is raised, the series resistance between the inner and outer base regions will increase, inevitably prolonging the delay time of the transistor.